The present invention relates generally to flip-flop circuits and more specifically to a circuit for preventing a metastable output state when the data input is asynchronous.
Latching circuits, such as flip-flops, are often used to synchronize signals that are operating at a different frequency than the system clock signal. Synchronous circuits usually require the system clock to define precisely when events can occur. Events can occur once per clock cycle at a specified point in the clock period known as the triggering edge. These circuits perform reliably if the input signals are stable for specified times before and after every triggering edge. These specified times are called the set up and hold times. When the set up and hold conditions are violated, the output response of the flip-flop is uncertain. The output may assume a metastable state in which the output of the digital logic circuit is not at a logic level 1 or a logic level 0, but instead is at an output level between logic level 0 and logic level 1. In asynchronous circuits, this problem occurs quite often. The output goes into a metastable state when the signal being input to the flip-flop undergoes a transition from one logic level to the other simultaneously with the triggering edge of the clock pulse. Once in a metastable state, the output can oscillate for an indefinite time, or suddenly switch after an indefinite time. The output becomes unpredictable and can generate random failures in a digital system.
There have been many attempts in the prior art to eliminate the problem of metastability in latching circuits. For example, U.S. Pat. No. 4,929,850 to Breuninger employs two flip-flops in series to reduce the chance of metastability. There is a timing relationship between the two flip-flops such that the propagation time of the first flip-flop input to its high output level plus the set up time of the second flip-flop must be less than the minimum propagation delay time of the clock between the clock input to the first flip-flop and the clock input to the second flip-flop. Other circuitry, such as described in U.S. Pat. No. 5,789,945 to Cline, and U.S. Pat. No. 5,081,377 to Freyman, aim to reduce length of the metastable state by using a feedback system. Other circuits, such as the circuits described in U.S. Pat. No. 5,489,865 to Colvin, Sr., U.S. Pat. No. 5,999,029 to Nguyen et al., and U.S. Pat. No. 4,999,528 to Keech, attempt to prevent the simultaneous assertion of more than one input signal using a combination of logic gates as pre-filter. The circuit described by U.S. Pat. No. 5,036,221 to Brucculeri et al., tries to eliminate meta-stable event using an edge detector as an early warning signal to disable/reenable the clock input.
It is the object of the present invention to provide a simple circuit to minimize the problem of metastability.
The above object has been met by a flip-flop having metastability reduction. The newly provided flip-flop uses two flip-flops connected in a parallel configuration with an offset or delay connected to the data input of the first flip-flop. The outputs of the two flip-flops are combined and it is expected that this will increase the probability that the output of at least one of the flip-flops will be stable. Thus, when the output of one of the flip-flops goes into a metastable state, the output of the other flip-flop will be stable. When the outputs of the flip-flops are combined, the combined output should follow the output of the stable flip-flop such that the overall output of the circuit is stable. Thus, the effect of the metastability is minimized.